1. Field of the Invention
The disclosed embodiments relate to back end of the line (BEOL) metal wires and, more particularly, to a wiring structure and method of forming the wiring structure with a conductive diffusion barrier layer having a relatively thick upper portion and relatively thin lower portion in order to allow for technology scaling without a significant corresponding increase in electromigration (EM) in the wiring structure, in time-dependent dielectric breakdown (TDDB) between wiring structures and induced by metal ion diffusion, or in wiring structure resistivity.
2. Description of the Related Art
Back end of the line (BEOL) metal wires have different optimal centering points depending upon the fault mechanism at issue. Specifically, the optimal ratio of the width of each wire to the width of a dielectric material in the space between two adjacent wires (i.e., the optimal wire width to dielectric space width ratio) for opens, for electromigration (EM) and for time dependent dielectric breakdown (TDDB) is different from the optimal wire width to dielectric space width ratio for shorts and for parasitic capacitance. Thus, integrated circuits are typically designed with a wire width to dielectric space width ratio that balances these competing factors. However, as operational voltages and wiring densities increase with advances in integrated circuit technologies, EM and TDDB, particularly in the case of copper (Cu) wires in a low-k interlayer dielectric material, have become major concerns. Specifically, increases in operational voltages and decreases in the distance between adjacent copper wires have resulted in increasingly higher electric fields between the adjacent copper wires and increasingly higher current densities inside the copper wires. Over time, high electric fields can result in copper ion (Cu+) diffusion and, thereby poor TDDB. Overtime, high current densities can result in EM degradation. Both TDDB and EM can lead to eventual device failure. It should be noted that EM is of increasing concern with device size scaling. Specifically, from one technology node to the next, the metal wire cross-section is scaled in size by roughly 70%, however, circuit voltage and diffusion barrier thickness are typically not scaled at the same rate. Consequently, the current density imposed on a scaled metal wire is greater and, thus EM is increased.
TDDB can be minimized by lining wiring trenches with a thick diffusion barrier layer. However, when the technology is scaled in size, the thickness of the diffusion barrier layer is also uniformly scaled in size so that the desired wire width to dielectric space width ratio is maintained. Thus, size scaling generally results in a corresponding increase in TDDB. Therefore, there is a need in the art for a wiring structure and a method of forming the structure that allows for technology scaling without a significant corresponding increase in TDDB.